Learning Resource and Development

ACM transactions on design automation of electronic systems.

Contributor(s): Material type: Continuing resourceContinuing resourcePublisher: New York, NY : Association for Computing Machinery, 2017Description: volumes : illustrations ; 25 cmContent type:
  • text
Media type:
  • unmediated
Carrier type:
  • volume
ISSN:
  • 1084-4309
Subject(s): Genre/Form: LOC classification:
  • TK7869 .A25
Available additional physical forms:
  • Also issued in an annual CD-ROM.
Incomplete contents:
Hierarchical dynamic thermal management method for high-performance many-core microprocessors -- Error-correcting sample preparation with cyber physical digital microfluidic lab-on-chip -- State assignment and optimization of ultra-high-speed FSMs utilizing tristate buffers -- A framework for block placement, migration, and fast searching in tiled-DNUCA architecture -- Obstacle-avoiding wind turbine placement for power loss and wake effect optimization -- Hardware trojans: lessons learned after one decade of research.
HoPE: hot-cacheline prediction for dynamic early decompression in compressed LLCs -- PeaPaw: performance and energy-aware partitioning of workload on heterogenous platforms -- CDTA: a comprehensive solution for counterfeit detection, traceability, and authentication in the lot supply chain -- Generation of transparent-scan sequences for diagnosis of scan chain faults -- Application-specific residential microgrid design methodology -- Layers assignment of escape buses with consecutive constraints in PCB Designs.
Exploring energy- efficient cache design in emerging mobile platforms -- Scalable bandwidth shaping scheme via adaptively managed parallel heaps in manycore-based network processors -- Optimal scheduling ad allocation for IC design management and cost reduction -- Proof-carrying hardware via inductive invariants -- Automated integration of dual-edge clocking for low-power operation in nanometer nodes -- Design methodology of fault-tolerant custom 3D network-on-chip.
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Holdings
Item type Current library Shelving location Call number Vol info Copy number Status Notes Date due Barcode
Serials Serials Main Library Serials Ser ENGR 25 v.22 n.1 2017 (Browse shelf(Opens below)) 2017 Volume 22, Number 1 1-4 Not For Loan Journal 01548S
Serials Serials Main Library Serials Ser ENGR 25 v.22 n.2 2017 (Browse shelf(Opens below)) 2017 Volume 22, Number 2 2-4 Not For Loan Journal 01180S
Serials Serials Main Library Serials Ser ENGR 25 v.22 n.3 2017 (Browse shelf(Opens below)) 2017 Volume 22, Number 3 3-4 Not For Loan Journal 00292S
Serials Serials Main Library Serials Ser ENGR 25 v.22 n.4 2017 (Browse shelf(Opens below)) 2017 Volume 22, Number 4 4-4 Not For Loan Journal 00219S

Includes bibliographical references

Hierarchical dynamic thermal management method for high-performance many-core microprocessors -- Error-correcting sample preparation with cyber physical digital microfluidic lab-on-chip -- State assignment and optimization of ultra-high-speed FSMs utilizing tristate buffers -- A framework for block placement, migration, and fast searching in tiled-DNUCA architecture -- Obstacle-avoiding wind turbine placement for power loss and wake effect optimization -- Hardware trojans: lessons learned after one decade of research.

HoPE: hot-cacheline prediction for dynamic early decompression in compressed LLCs -- PeaPaw: performance and energy-aware partitioning of workload on heterogenous platforms -- CDTA: a comprehensive solution for counterfeit detection, traceability, and authentication in the lot supply chain -- Generation of transparent-scan sequences for diagnosis of scan chain faults -- Application-specific residential microgrid design methodology -- Layers assignment of escape buses with consecutive constraints in PCB Designs.

Exploring energy- efficient cache design in emerging mobile platforms -- Scalable bandwidth shaping scheme via adaptively managed parallel heaps in manycore-based network processors -- Optimal scheduling ad allocation for IC design management and cost reduction -- Proof-carrying hardware via inductive invariants -- Automated integration of dual-edge clocking for low-power operation in nanometer nodes -- Design methodology of fault-tolerant custom 3D network-on-chip.

Bachelor of Science in Electronics Engineering BSEE (CEA)

Also issued in an annual CD-ROM.

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